Many integrated circuits have chip function identification codes programmed into the chip. The identification codes often take the form of thirty-two (32) bit codes that are programmed into the chip's circuitry by selective connection of individual pins within the IC to VSS or VDD to represent data “0” or “1”, respectively. The pins are connected to internal data circuitry, such as a register, formed in the substrate that can be accessed to read the 32 bit code programmed into the chip. In these prior art chips, each bit design has a horizontal strap with contacts and links on all metal levels. Each strap represents one metal level where the links can be removed and added depending on the setting of the bit to VDD (high) or VSS (low).
FIG. 1 is a top view of a chip having a chip function identification layout using links within the metal layers for Bit 31 through Bit 0. All metal layers are shown. The area assigned to one bit is labeled as such in FIG. 1. FIG. 2 is an enlarged view of the bit area shown in FIG. 1. The VSS and VDD rails are labeled as such. FIG. 3 is a cross-sectional representation of one bit area. FIG. 3 shows a pin formed at Metal 3 that is connected by a circuit path (not shown) to substrate circuitry (e.g., a register) (also not shown). FIG. 3 also illustrates Metal and Via layers 1 to 7. Metal links 10 shown in FIG. 3 are selectively provided or not provided on a specific metal level in order to set the bit of the chip ID to either LOW/VSS or HIGH/VDD, i.e., to selectively connect the pin for that bit to VSS or VDD. Setting the links 10 in this design is complex, since the designer must be sure to add and remove the correct metal link in the correct horizontal strap. Further, as new versions of the chip are released, new chip function identification codes are assigned to the new versions. Since the codes are programmed into the chip using links 10 within the various metal connection layers, a new mask or masks (in some circumstances) is required to incorporate the change in links needed to change the programmed bits of the code. This is required even if the change in chip functionality did not necessitate a change to the structure of the metal/via connection layers. As those in the art will recognize, these metal layer masks are quite expensive, often costing $50,000 or more each, and difficult to design.
New layout structures for programming chip identification function codes and other information are desired.